Polycrystalline semiconductor alloy films have found great utility in the field of photosensitive devices, electronic imaging devices, and thin film transistors (TFT's). In particular, polycrystalline semiconductor alloy films have been investigated for use in TFT's for application as switching elements for large area, multipixel liquid crystal displays and image sensors.
Structurally, TFT's generally include source and drain electrodes, source and drain contact regions, a body of semiconductor alloy material between the source and drain electrodes, and a gate electrode in proximity to the body of semiconductor material, but insulated therefrom by a gate insulator. A typical enhancement mode thin film transistor is described in detail hereinbelow. Current in a TFT typically flows through the transistor, between the source and drain, and is controlled by the application of a voltage to the gate electrode. The voltage on the gate electrode produces an electric field which accumulates a charged region near the semiconductor body-gate insulator interface. This charged region forms a current conducting channel in the body of semiconductor material through which the device current is conducted.
In the fabrication of thin film transistors, source and drain regions should be rectifying if the body of semiconductor material is intrinsic, and ohmic if the body of semiconductor material is of opposite conductivity type than the source and drain. The resistivity of the source and drain contact regions should be as low as possible to reduce the loss of input signal. The source and drain contacts of TFT's are typically fabricated of thin metal layers deposited upon either p-doped or n-doped amorphous or polycrystalline semiconductor alloy films.
As used herein, the term "body of semiconductor alloy material" refers to a film of amorphous, polycrystalline or microcrystalline semiconductor material fabricated from silicon, silicon alloys, silicon:germanium alloys, germanium alloys, germanium, gallium arsenide, copper indium diselenide, carbon and combinations thereof. The term "doped layers of amorphous semiconductor alloy material" refers to doped layers of p-type or n-type amorphous material fabricated from silicon, silicon alloys, silicon:germanium alloys, germanium alloys, germanium, gallium arsenide, copper indium diselenide, carbon and combinations thereof. It is to be understood that silicon:germanium alloys include all combinations and ratios of silicon and germanium.
Many different deposition techniques have been employed in order to fabricate doped layers of amorphous semiconductor alloy material for use in, for example, the source and drain regions of thin film transistors. One such technique involves depositing a body of semiconductor alloy material upon a substrate, as by conventional deposition processes, and which deposited material is then subjected to an ion implantation technique to dope at least a portion of the body of semiconductor alloy material so as to define source and drain regions. However, ion implantation has several inherent disadvantages which make its use for fabrication of doped layers of semiconductor alloy material impractical, particularly for large-scale, commercial applicators, such as the commercial fabrication of, e.g., displays, and photosensitive devices employing such TFT devices. These inherent disadvantages include: (1) the radius of the ion beam used to implant a desired dopant is generally quite small, thus requiring that the ion beam be repeatedly scanned in order to attain complete coverage over a wide area sample; (2) ion implantation devices are generally very difficult to scale up to large area, continuous throughput production processes such as is required in the commercialization of a product employing TFT's; (3) said ion implantation devices typically require large magnetic fields as well as high vacuum, low pressure regimes for operation; these parameters significantly increase both the initial purchase cost of such devices, as well as the cost of operating such devices; and (4) ion implantation, due to high energy impact of the implanted ions, causes significant physical damage to the body of semiconductor alloy material, thus necessitating a subsequent annealing process to repair the damage. This anneal/repair process may be too physically stressful for some types of low temperature substrates, such as low temperature glasses.
A second technique which has been employed for the fabrication of doped layers of amorphous semiconductor alloy material is the use of conventional deposition processes, such as sputtering, or r.f. glow discharge plasma deposition, to form a multilayered amorphous structure. The multilayered amorphous structure may subsequently be at least partially crystallized, as by conventional techniques such as thermal anneal, to form polycrystalline or microcrystalline layers. By this method, substantially intrinsic amorphous silicon alloy material is deposited by, for example, r.f. glow discharge from silane with an added compensating element or elements such as hydrogen, fluorine or both. Deposited upon the semiconductor alloy material is a second layer of amorphous semiconductor alloy material, which second layer is doped so as to possess either p or n-type conductivity. Doping of the second layer is achieved by the addition of a precursor dopant gas to the deposition gases present in the r.f. glow discharge deposition chamber. After depositing such layers, unwanted areas of said doped material may be removed, as by conventional photolithographic techniques to form desired device features.
While this technique has the advantage of being relatively easy in terms of actual deposition, devices formed in this way are inherently inferior to those produced by, for example, costlier ion implantation techniques. Multilayered devices fabricated by conventional plasma deposition techniques potentially demonstrate significant peeling problems between the stacked layers as well as other interfacial defects. The interface between said layers, e.g., between the semiconductor body and the source or drain regions, gives rise to a significant density of defect states, which states significantly decrease the performance of the device. A gradual gradation from intrinsic to n-type to heavily n-type would greatly reduce the density of defect states, and therefore improve device performance.
A third technique which may be employed to form doped layers of amorphous semiconductor alloy material is an "ion shower" technique such as that discussed by Yoshida, et al in "Formation of Source and Drain Regions for Amorphous Si:H Thin-Film Transistors by Low Energy Ion Doping Techniques" published in IEEE Electron Device Letters, Vol. 9, No. 2, Feb. 1988. While this technique possess several advantages over conventional ion implantation, notably the ability to act over a larger area than regular ion implantation, it still possesses several disadvantages, particularly the need for magnetic fields. Further, Yoshida, et al require a high vacuum, low pressure regime in order to accelerate dopant ions sufficiently to implant them into the host material.
One shortcoming inherent in each of the aforementioned techniques is the high annealing temperatures required to activate the dopant ions within the body of semiconductor alloy material to provide electrical activity. Activation of the doped layer of amorphous semiconductor alloy material includes exposing said materials to a temperature regime sufficient to at least partially crystallize the amorphous materials, i.e., form a poly or microcrystalline structure, while incorporating the dopant element into the matrix of the semiconductor alloy material. This is critical since techniques requiring high activation temperatures necessitate the use of expensive, high temperature resistant glass substrates such as Hoya NA40 display glass. Such high temperature substrates greatly increase the cost associated with fabricating electronic devices such as imaging arrays.
It thus becomes apparent that a need exists for a deposition method which allows for easy, economical fabrication of doped polycrystalline semiconductor alloy material, at relatively low temperatures.